Frequency dividers are commonly used to reduce the frequency of a clock signal in an integrated circuit by a factor of an integer, for example, 2, 3, 4, 6, and so forth. The reduced frequency clock signal may be used, for example, in a circuit that cannot operate at the reference clock signal frequency and instead operates at a lower frequency (e.g., a memory).
The reduced frequency clock signal may also be used in a circuit that can operate at the reference clock signal frequency, but that alternatively operates at a reduced frequency—for example in a low-power mode of operation. The selective use of the reduced frequency in these circuits allows for lower dynamic power consumption because of the less frequent transitioning of the clock signal, while still allowing a clock signal with the same frequency as the reference clock signal to be used when needed. In those devices that selectively use such a reduced frequency, a frequency divider or other circuit may be needed that can alternate between providing a common frequency clock signal (e.g., a clock signal that has the same frequency as the reference clock signal) and the reduced frequency clock signal. A circuit such as a multiplexer can be used in the frequency divider to select between providing the common frequency clock signal and the reduced frequency clock signal.
In providing the reduced frequency clock signal, the frequency divider typically introduces a propagation delay into the reduced frequency clock signal path as compared with the common frequency clock signal path. If the propagation delay of the reduced frequency clock signal is different than the propagation delay of the common frequency clock signal, a circuit that alternatingly receives the reduced frequency clock signal and the common frequency clock signal may not operate as intended due to the common frequency clock signal being out of phase with the reduced frequency clock signal. In order to try to match the delay of the common frequency clock signal propagation path with the reduced frequency clock signal propagation path, a model delay element can be used in the common frequency clock signal propagation path. However, the delay matching may be inaccurate in different operating conditions and across variations in the manufacturing process.
Furthermore, frequency dividers with two signal propagation paths, a model delay element, and a multiplexer to select between the two signal propagation paths may consume a large amount of power and introduce a relatively large propagation delay into both clock signal propagation paths (for example, a six gate delay). The large amount of power and the relatively large propagation delay may be unacceptable in some applications.